IC Physical Design Engineer

As part of OPENCHIP & SOFTWARE TECHNOLOGIES IC Design group, you will design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC) AI accelerators. The target product is a series of AI-specific semiconductor systems designed to deliver low power consumption and high-performance chips providing efficiency in machine learning and deep learning applications. These chips are used in various industries, including HPC, security, manufacturing, mobility, automotive, and more.
·As a IC Physical Design Engineer, you will be responsible for all aspects of physical design and implementation of AI accelerator SoC in deep submicron CMOS technology. You will participate in establishing physical design methodologies, flow automation, chip floorplan, power/clock distribution, chip assembly and P&R, timing closure. You will drive static timing analysis, power and noise analysis and back-end verification. Drive, in close collaboration with the digital front-end and back-end team, the specifications of the IC digital sub-blocks to get the best area/power trade-off. You will contribute to the design and verification methodology at chip level and sub-blocks level. You will define the test strategy of the digital part(s) under responsibility and drive its implementation and participate to the evaluation of the fabricated IC.

  • Lead and support digital design work-packages from RTL to GDSII
  • Experience in physical design, preferably with high performance designs.
  • Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications.
  • Understanding of Design for Test methodologies and DFT verification experience (Scan Stitching, memory BIST etc.).
  • Experience in automated design flows for clock tree synthesis, clock and power gating techniques, design optimization for improved timing/power/area, and design cycle time reduction.
  • Experience in floorplanning, establishing design methodology, IP integration, checks physical/timing/electrical quality, and final signoff for large IP delivery.
  • Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation.
  • Versatility with scripts to automate design flow.
  • Good understanding of computer organization/architecture is preferred.