As part of OPENCHIP & SOFTWARE TECHNOLOGIES System Architecture group, you will design and manufacture our next-generation, high-performance, power-efficient, system-on-chip (SoC) AI accelerators. The target product is a series of AI-specific system designed to deliver low power consumption and high-performance chips providing efficiency in machine learning and deep learning applications. These chips are used in various industries, including HPC, security, manufacturing, mobility, automotive, and more.
Your role will be as Memory Controller Micro-Architect/Logic Designer, contributing to the RISC-V micro-architecture development and logic design of custom Memory controller IP. You will interact with the system architects, performance/power, and design implementation teams to drive the RTL design, performance and power optimization, logic debug and timing closure of the design. You will work with the verification team to verify the functionality and correctness of the design and collaborate with the physical design and CAD team to resolve implementation level details.
- Deep understanding of memory controller and experience in HBM/DDR4/5, LPDDR memory technology.
- Memory system design experience, driving the RTL design of various sub-blocks of memory controller and cache mechanisms for high-performance digital designs.
- Experience with hardware memory management unit, prefetching, or memory subsystems.
- Experience analysing benchmarks, application workloads and performance simulation results to identify areas for memory access optimizations.
- Practical experience with multi-core systems and memory interconnection.
- SystemVerilog/Verilog expertise is required.
- Deep understanding of SoC design flow (e.g., Specification, Architecture, RTL coding, Verification, DFT, Synthesis, Power and Timing analysis, floor planning).
- Experience with high frequency design considerations (timing, power, multiple clock domains, etc.).
- Background in physical design and knowledge of advanced process technology is a plus.