Design Verification Engineer

As part of OPENCHIP & SOFTWARE TECHNOLOGIES IC Verification group, you will design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC) AI accelerators. The target product is a series of AI-specific semiconductor systems designed to deliver low power consumption and high-performance chips providing efficiency in machine learning and deep learning applications. These chips are used in various industries, including HPC, security, manufacturing, mobility, automotive, and more.
·As a Design Verification Engineer, you will be part of a dynamic company focused on developing innovative AI accelerator solutions. You will be responsible for verification of the ASIC design, architecture, golden models and micro-architecture using advanced verification methodologies such as UVM. Along with traditional simulation, you will be able to use other approaches like Formal Verification and Emulation to achieve a bug-free design. The role also implies collaboration with software developers, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success.

  • Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle.
  • Experience in development of UVM based verification environments from scratch and experience with Design verification of AI related applications (AI/ML/NN). Experience in EDA tools and scripting (Python, Perl) used to build tools and flows for verification environments.
  • Experience in SystemVerilog/Verilog/UVM methodology and/or C/C++ based verification.
  • Experience in IP/sub-system and SoC level verification based on SystemVerilog UVM/OVM based methodologies.
  • Experience on SoC design flow (e.g., Specification, Architecture, RTL coding, Verification, DFT, Synthesis, Power and Timing analysis, floor planning).
  • Experience with high frequency design considerations (timing, power, multiple clock domains, etc.).